The following files were generated for 'chipscope_cpu_vio' in directory
F:\PDPx\pdp10\KS10\fpga\rtl\xilinx\chipscope_cpu_vio\

XCO file generator:
   Generate an XCO file for compatibility with legacy flows.

   * chipscope_cpu_vio.xco

Creates an implementation netlist:
   Creates an implementation netlist for the IP.

   * chipscope_cpu_vio.cdc
   * chipscope_cpu_vio.ngc
   * chipscope_cpu_vio.v
   * chipscope_cpu_vio.veo

Creates an HDL instantiation template:
   Creates an HDL instantiation template for the IP.

   * chipscope_cpu_vio.veo

IP Symbol Generator:
   Generate an IP symbol based on the current project options'.

   * chipscope_cpu_vio.asy

SYM file generator:
   Generate a SYM file for compatibility with legacy flows

   * chipscope_cpu_vio.sym

Generate ISE metadata:
   Create a metadata file for use when including this core in ISE designs

   * chipscope_cpu_vio_xmdf.tcl

Generate ISE subproject:
   Create an ISE subproject for use when including this core in ISE designs

   * _xmsgs/pn_parser.xmsgs
   * chipscope_cpu_vio.gise
   * chipscope_cpu_vio.xise

Deliver Readme:
   Readme file for the IP.

   * chipscope_cpu_vio_readme.txt

Generate FLIST file:
   Text file listing all of the output files produced when a customized core was
   generated in the CORE Generator.

   * chipscope_cpu_vio_flist.txt

Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.

