Terms This document contains the requirements for the project, which have been copied from the job description: I need a simple Verilog LPDDR2 memory Controller for the Cyclone V GX Starter kit. This FPGA evaluation board has an on-board Micron MT42L128M32D1LF-25 WT:A LPDDR2 memory chip. I need to access this chip from Verilog using a simple SRAM-like interface. This memory controller should be your own design, or a modified open-source one whose license allows for modification and distribution. The user side interface should be simple and allow for reads and writes as seen below. (for writing) 1. Place an address on the bus. 2. Place the data on the bus. 3. Set read/write direction to write. 3.5 Initiate the write. 4. Wait for confirmation that write completed (for reading) 1. Place an address on the bus. 2. Set read/write direction to read.\ 2.5 Initiate the read. 3. Wait for signal saying data on bus is now valid. Status signals about the current state of the memory controller should also be available. The deliverable should be a Quartus project (.qpf), a settings file (.qsf) containing the necessary pin assignments/voltage levels/signal direction/etc for the GX Starter board, a timing-constraints file (.sdc) the associated Verilog source modules, and anything else required to successfully compile and deploy. The first module should be the controller module. The second module should be the top module showing how to instantiate the controller module, how to initialize it (if necessary), and then a loop that writes a fixed value into the RAM, and then a loop that reads back the RAM verifying that the fixed value has been found in the locations. LEDs or 7-segment displays should be used to indicate status of the test, current significant bytes of the address, and so on. These modules must compile using the latest Quartus II version 15.0 for Windows, and the test module must successfully run on the evaluation board without error. The delivered solution should be ready to compile AS-IS, and deploy on the board. The modules should be reasonably commented in English, and the source should be fully visible. I've attached the memory datasheet, and the user manual for the FPGA evaluation board. *Additional requirements* The speed grade of the memory chip on the GX eval board is -25, so the target frequency for the controller should be 400mhz. One of the goals will be making sure that all the timing requirements are met. If we can't achieve 400mhz for the controller, then we can relax that goal --- but having the fastest reliable memory controller is key. The absolute minimum clock rate should be 300mhz. This controller should be efficient, and not consume a ton of logic resources. The target ALM count on the Cyclone V should not exceed approximately 1500 ALMs. There must be some consideration given for how to use this controller in a practical environment and I'll need help in understanding what key feature(s) might be required to make it usable. Timely support to get this functional on the eval board after delivery is considered part of the requirement, and is the best measure of success. This controller should support non-simultaneous access from multiple processes, so there should be some mechanism that allows multiplexed access. Perhaps either front-ending it with a MUX or using a bus-like architecture. Micron provides Verilog memory models to aid in the simulation of associated controllers. An additional ModelSim test bench that uses Micron's memory models for simulation should be included. Support should be included for different burst modes: (as compile-time parameterization): All three memory-supported Burst lengths are required: 4, 8, and 16. If the ModelSim testbench or burst mode support cannot be delivered "error-free" in a reasonable time-frame, we will negotiate a discount in the final milestone.