keithSo tonight I fooled around with ISIM, which is Xilinx’s simulator. I was doing behavior simulation and wrote a small testbench for the block ram state machine that I wrote a few days ago.
Really neat stuff.
Xilinx’s ISE really makes it easy for you because it will create a testbench fixture of any module automatically. This type of help and framework template is simply invaluable. It gives you a fantastic starting point, and I really need a push in the right direction for most of this. It’s not as if I wouldn’t have figured it out, but it simply does it for you. And the more and more I look thru ISE, the more I find this to be true. Nice, useful things although you’ve got to look for them.
Reminds me of photoshop in lots of ways. Photoshop hides theirs……ISE leaves in plain sight, along w/ 45000 other options. 🙂
Pretty neat to watch the state machine switch states based on counter rollovers, etc….. I’m surprised it handles trillions of picoseconds of time so quickly… I’ve got a nice machine, but it really doesnt get bogged down despite all of the “entries”
It’s almost 2am local time so I better go to bed. But this simulation stuff is definitely neat. It lets you test this stuff w/o running it on the actual hardware……
Hi,
I’m new to hdl. I just designed a RAM based state machine and need to simulate it in ISim. I prepared the verilog test fixture and simulated my design but it gives ‘X’ on all outbuts of the RAM. Can you provide me the copy of your Testbench file (VHDL or Verilog) so that I can debug my test fixture. I think I have not declared the UUT properly as I do not see the RAM file under the Testbench file in the Design Hierarchy window in ISE. And the strange thing is that the same testbench file works fine with another ROM module. I would appreciate if you could mail me your testbench file to Kaushik_r_lathia (at) yahoo (dot) com. Thanks