Minimig - An Amiga in an FPGA
What is Minimig?
Minimig stands for Mini Amiga. Minimig is an FPGA-based re-implementation of the original Amiga 500 hardware. In it's current form, Minimig is a single PCB measuring only 12*12cm which makes it the smallest "Amiga" ever made and the first new "Amiga" in almost 14 years! Minimig is available for download as an open-source / open-hardware design under the GNU public license. This page describes the architecture and the inner working of the Minimig. All design files can be downloaded from the download section.
History
The idea to make Minimig started around january 2005. The C64DTV had just been released and the Amiga forums were buzzing disccussing the possibility of putting a complete Amiga with games inside a single joystick.
Things like ASIC's, FPGA's and VHDL were discussed and being a hardware engineer, they immediately caught my attention. I remember that the discussions ended with the conclusion that it should be possible to put an Amiga in a joystick but that it would be a very difficult task. The first step of such an undertaking would be to reverse engineer the Amiga chipset and get it running inside an FPGA.
The following weeks I discussed this idea with a collaegue who also happened to be an Amiga enthusiast. He did some FPGA programming during his previous job. The more he told me about FPGA's and the more I dug into my old Amiga literature, the more I became convinced that it could indeed be done. And so it started, I learned Verilog, bought an FPGA board and started coding! It took me almost a year to get the Minimig to boot it's first game (which was Lemmings, by the way). It was and is the largest hobby project I have ever started.
The first version of Minimig was built around a Digilent Spartan-3 FPGA starter board, which I expanded with a real 68000, an upgraded vga output and a PIC-controller based floppy emulator. That version can be seen in the picture to the left. Later I moved the design to it's own custom-designed PCB which I called rev1.0. That is the version that is described here.
Minimig rev1.0 technical description
The Minimig rev1.0 is built on a single 12*12cm PCB that contains all components to make up a complete Amiga. It has no floppy drive or harddisk. Instead it is equipped with a MMC flash card slot and a microcontroller based floppy emulator. The flash card holds the disk-images which can be "loaded" into the Minimig using a convenient on-screen-display.
The (physical) hardware of the Minimig consists of 4 major parts:
The FPGA
The 68000
The RAM
The PIC controller
The FPGA
The FPGA is the heart of the Minimig. The FPGA used is a 400Kgate Spartan-3 by Xilinx. All the other major components (RAM and 68000) connect directly to the FPGA. The FPGA implements the Amiga custom chips Denise, Agnus, Paula and Gary as well as both 8520 CIA's. It also implements a simple version of Amber so that VGA monitors can be connected. Besides this, the FPGA also acts as an automatic joystick-mouse-switcher, a PS2-to-Amiga-keyboard converter, PS2-to-Amiga-mouse converter and as an OSD (on-screen-display) generator. All of these function were not present in the original Amiga, but make life much easier now that we are living in the 21th century! The Spartan-3 is a ram-based FPGA and must be loaded with a "core" upon startup. This is done by the PIC controller described below.
The 68000
The 68000 is the Minimig's main processor. The Minimig uses a special version of the 68000: the MC68SEC000. This version runs at 3.3V and is completely static (so it can run at any frequency between 0 and Fmax). This makes it an excellent companion for the Spartan-3 FPGA as there is no need for level-shifting between 3.3V and 5V levels. The MC68SEC000 connects directly to the FPGA.
The RAM
The Minimig rev1.0 board contains 2Mbyte of 70ns static ram. The RAM is organised as 2 524288*16 banks. Each bank has seperate enables for the upper and lower byte. The RAM is used to implement the 3 types of memory needed by the Minimig, namely: kickstart rom area, chip ram and (ranger) fast ram. As the Minimig has no kickstart socket, the kickstart image must be loaded upon startup. This is done by the PIC controller described below. Once loaded, writes to that area of the RAM are disabled and the area acts like a read-only memory. The remaining part of the RAM (1.5Mbyte) is divided up between chip and fast ram.
NOTICE: The ST RAM chips used in Minimig rev1.0 are obsolete. If you want to build a Minimig rev1.0, please check the availability of all used parts first. A suitable replacement for the ST type is the ISSI IS62WV51216BLL-55TLI. These chips can still be bought from Digikey (part number 706-1048-ND)
The PIC controller
The PIC controller fullfills the role of "bios". It is a single chip 8-bit microcontroller from Microchip. The PIC controller configures the FPGA (by loading a core into it), loads the kickstart image into the kickstart ram area and acts as an Amiga floppy emulator. Thus, the PIC controller really starts the system up as soon as power is applied, hence the "bios"-like function. The Minimig uses a PIC controller type 18LF252/SP.
FPGA general internal architecture
Besides the physical hardware, there is the "programmed" hardware inside the FPGA. This hardware is described in Verilog. To keep the project manageable I have kept the same organization as a real Amiga. That is, I have kept the Denise functions in a Denise module, Agnus functions in an Agnus module etc. I have even kept a lot af the signal names the same, so there is a dmal signal (as well as an extra dmas signal), an int2 signal, an ovl signal and so on. Besides these standard modules, there are also 2 bridge modules to connect the FPGA hardware to the RAM and 68000 chips. The code for the FPGA has been synthesized using the free webpack tool V9.1i from Xilinx.
FPGA internal bus structure and clocking scheme
This needs some explanation as it is quite different from a real Amiga 500. Whereas the Amiga 500 had a seperate chipram bus and fastram bus, the Minimig has only a single, synchronous multiplexed bus. To compensate for this, this bus is clocked at 7.09379MHz or twice the speed of an PAL Amiga 500 bus. This clock is the Minimig's main clock (called "clk" in the code). It is the clock far ALL Minimig sub-systems, including the CIA's. As the CIA's are normally run at the so-called E clock (709379Hz), special circuitry has been added to Gary to slow down CPU accesses to the CIA's to approximately E clock speed. Clk is also used as the Minimig's pixel clock. For hires screen-modes clk is "double-pumped", with new pixels put out at both the rising edge and the falling edge of clk giving an effective pixel rate of 14.18758MHz. Besides clk, two other clocks are generated; qclk and vgaclk. Qclk is clk shifted by 90 degrees. Qclk is used by the SRAM bridge to control read/write timing. Vgaclk is used as the pixelclock for the Amber scandoubler module. All clocks are derived from a single 4.433619MHz PAL crystal using the FPGA's DCM module (Digital Clock Manager).
The Minimig internal bus is used as both the chipram bus and fastram bus. All modules (including kickstart area and CIA's) connect to this bus. This bus is time-multiplexed between chipram and fastram/kickstart/CIA's. The mulitplexing is controlled by Agnus and the horizontal pixel counter "horbeam". The lower 2 bits of horbeam define 4 types of bus "slots":
slot 2'b00: fastram (68000)
slot 2'b01: chipram (disk, bitplanes, copper, blitter and 68000)
slot 2'b10: fastram and blitter (non-standard, gives cpu some more cycles in chipram to fix some compability problems)
slot 2'b11: chipram (disk, bitplanes, sprites, audio and 68000)
The Agnus module passes the signals dma,dmapri and dmawr to the Gary module to indicate the type of bus slot. Dma indicates that Agnus is doing a bus cycle (read or write) and dmawr indicates that that cycle is a write cycle. Dmapri indicates that Agnus only holds the bus bus does not write or read it (Agnus does a "dummy cycle). If both dma and dmawr are inactive, the CPU can use the bus if it wants to.
Because the FPGA does not supports internal tri-state busses, all devices are connected together using 'or" gates. The convention is thus as follows; when a device is not selected, it drives it's outputs low. When the device is selected, it drives it's outputs with the data it wants to write.
Boot sequence
The boot sequence is a 2-step process. The first step is to configure the FPGA. Like said, this is done by the PIC controller. The second step is to load the Kickstart image. This is done as follows;
Once the FPGA is configured, the system is booted in a special state. In this state, a small bootrom is overlayed at addresss #0. This bootrom loads the kickstart through the floppy emulator. Once the kickstart has been loaded, the bootrom resets the system. The bootrom then disappears from address #0 and the system boots as if it were a normal Amiga. The code from the bootrom is written in 68000 assembly. I have used the freeware AS32 assembler from the Freescale website. I have made it available for download here as I can't find it anymore on their (again...) redesigned website.
PIC controller firmware and FPGA to PIC communication
The PIC's firmware is written in Hi-Tech Ansi C. The firmware contains MMC (Multi Media Card) and FAT16 drivers to control the flash card. The firmware also handles the user-interface and on-screen-display. The PIC communicates with the FPGA through an SPI interface. The MMC card is also connected to this SPI bus. In it's current form, the FPGA has 2 SPI "addresses". Address #0 is selected by the fpga_sel0 signal and control the floppy emulator. fpga_sel1 controls the on-screen-display. fpga_sel2 is currently unused.
Disclaimer 1: About the Kickstart
To function, Minimig needs a kickstart rom image. The Kickstart is a copyrighted piece of software. Therefore, you are not allowed to just download it anywhere from the web. You must own the original kickstart roms and make an image of them using the method described in the UAE archives.
Disclaimer 2: If you decide to built it...
Do so completely at your own risk. This is not a beginners project.
Minimig rev1.1 PCB
The minimig rev1.1 PCB is a minor update of the original rev1.0 PCB. It fixes some problems with the original PCB:
* The wire patch needed for rev1.0 to work is now incorporated into the layout. So, rev1.1 doesn't need a single wire patch!
* R49 has been decreased to 100 Ohm for better MMC-Card compatbility.
* The PS/2 connectors are now properly connected to the frame ground.
* The bottom silk screen has been cleaned up and added to the gerber file set.
Minimig rev1.1 is 100% core and firmware compatible with the rev1.0 PCB. Although it has not been built by me (and therefore has not been verified by me), it passes all design rule checks so I trust it will work. The rev1.1 PCB (like rev1.0) has been designed using rather "relaxed" design rules so any PCB manafacturer should be able to produce it.
Future
What does the future hold for Minimig? I don't know. My hope is that due to the GNU public license people will debug it, expand it and generally make it better. What I would like to see first is the implementation of some form of harddisk support, ethernet support and offcourse a debugged sprite engine :-). It would also be nice if the verilog sources of Minimig would make it into a sourceforge project. I could really need some help there. And the rest? Only time will tell!
Home
Minimig page1
Minimig page2
Gallery
Downloads
Links
Things like ASIC's, FPGA's and VHDL were discussed and being a hardware engineer, they immediately caught my attention. I remember that the discussions ended with the conclusion that it should be possible to put an Amiga in a joystick but that it would be a very difficult task. The first step of such an undertaking would be to reverse engineer the Amiga chipset and get it running inside an FPGA.
The (physical) hardware of the Minimig consists of 4 major parts: